1. Field of the Invention
The present invention relates to a regenerator and the regenerating method, particularly relates to a regenerator for regenerating information according to an inserted signal such as a synchronizing signal or an address signal periodically inserted into information recorded on a recording medium or information transmitted via a transmission medium and the regenerating method.
2. Description of the Related Art
In a conventional type recording medium recording regenerator, when digital data is recorded on a recording medium, it is recorded after the data is divided into frames of predetermined length and a synchronizing signal for showing the separation of an individual frame is inserted between frames.
In case such recorded data is regenerated, after information is read in units of frame from a recording medium, referring to a synchronizing signal and error correction and others are executed using the read frame as a basic unit, original data is regenerated.
Therefore, to precisely execute error correction for data read from the recording medium, in the conventional type recording medium recording regenerator, a synchronizing signal is required to be precisely detected and a frame functioning as a basic unit is required to be securely extracted.
FIG. 19 shows an example of the constitution of a resynchronizing device for detecting a synchronizing signal and correcting the timing of the detected synchronizing signal in a conventional type recording medium recording regenerator.
As shown in FIG. 19, a synchronizing signal detecting circuit 1 detects a synchronizing signal included in a regenerative RF signal read from a recording medium not shown. A synchronization judging circuit 2 judges whether the timing of a synchronizing signal is normal or not, referring to a window signal output from a window signal generating circuit 4. A reference counter 3 counts for example, from a value zero to a value 1000 repeatedly (returns to zero if a count value reaches 1000 and repeats counting) and supplies the output to the synchronization judging circuit 2 and the window signal generating circuit 4. The reference counter 3 is reset by a reset signal output from the synchronization judging circuit 2.
Referring to a count value output from the reference counter 3, the window signal generating circuit 4 changes a window signal to a high level at timing at which the output value is 990 and changes the window signal to a low level at timing at which the output value is 10. A resynchronizing signal output circuit 5 outputs a resynchronizing signal at timing at which a count value output from the reference counter 3 is zero.
Next, referring to flowcharts shown in FIGS. 20 to 22 and a timing chart shown in FIG. 23, operation in the prior example shown in FIG. 19 will be described.
FIG. 20 shows an example of processing that the synchronization judging circuit 2 shown in FIG. 19 executes. When this processing is executed, the synchronization judging circuit 2 judges whether a synchronizing signal is detected or not by the synchronizing signal detecting circuit 1 in a step S1. As a result, if it is judged that a synchronizing signal is not detected (NO), processing is returned to the step S1 and the same processing is repeated until a synchronizing signal is detected. If it is judged that a synchronizing signal is detected (YES), processing proceeds to a step S2.
In the step S2, the synchronization judging circuit 2 outputs a reset signal to the reference counter 3. As a result, a count value of the reference counter 3 is reset to zero. Next, processing proceeds to a step S3 and a variable N.sub.1 is initialized to zero.
In the next step S4, it is judged whether a synchronizing signal is detected by the synchronizing signal detecting circuit 1 or not. As a result, if it is judged that a synchronizing signal is not detected (NO), processing proceeds to a step S6. If it is judged that a synchronizing signal is detected (YES), processing proceeds to a step S5.
In the step S5, if a synchronizing signal is detected in a window, processing is returned to the step S2 and the same processing is repeated. If a synchronizing signal is detected outside a window, processing is returned to the step S4 and the same processing is repeated.
In the step S4, if it is judged that a synchronizing signal is not detected (NO), processing proceeds to the step S6. In the step S6, if a synchronizing signal is not detected in a window, processing is returned to the step S4 and the same processing is repeated. If a synchronizing signal is not detected outside a window, processing proceeds to a step S7.
In the step S7, the synchronization judging circuit 2 outputs a reset signal to the reference counter 3. As a result, a count value of the reference counter 3 is reset to zero.
In the next step S8, the value of the variable N.sub.1 is incremented by one. In a step S9, it is judged whether the value of the variable N.sub.1 is 4 or more or not and as a result, if it is judged that the value of the variable N.sub.1 is 4 or more (YES), processing is returned to the step S1 and the same processing is repeated. In the step S9, if it is judged that the value of the variable N.sub.1 is smaller than 4 (NO), processing is returned to the step S4 and the same processing is repeated.
FIG. 21 is a flowchart for explaining processing for generating a window signal. The processing is executed by the window signal generating circuit 4 shown in FIG. 19. When the processing is executed, the window signal generating circuit 4 judges whether a count value of the reference counter 3 is 990 or not in a step S20. As a result, if it is judged that a count value of the reference counter 3 is not 990 (NO), processing is returned to the step S20 and the same processing is repeated. If it is judged that a count value of the reference counter 3 is 990 (YES), processing proceeds to a step S21.
In the step S21, the window signal generating circuit 4 changes the output to a high level. Processing proceeds to a step S22 and the window signal generating circuit judges whether a count value of the reference counter 3 is 10 or not. As a result, if it is judged that a count value of the reference counter 3 is not 10 (NO), processing is returned to the step S22 and the same processing is repeated. If it is judged that a count value is 10 (YES), processing proceeds to a step S23.
In the step S23, the window signal generating circuit 4 changes a window signal to a low level. Processing is returned to the step S20 and the same processing is repeated.
The window signal generating circuit 4 is changed to a high level, generates and outputs a window signal shown in FIG. 23B by the above processing only while a count value of the reference counter 3 is between 990 and 1000 and between 0 and 10.
FIG. 22 is a flowchart for explaining processing executed in the resynchronizing signal output circuit 5 shown in FIG. 19 for generating a resynchronizing signal.
When this processing is executed, the resynchronizing signal output circuit 5 judges whether a count value of the reference counter is zero or not in a step S40. As a result, if it is judged that the value of the reference counter 3 is not zero (NO), processing is returned to the step S40 and the same processing is repeated. If it is judged that a count value of the reference counter 3 is zero (YES), processing proceeds to a step S41.
In the step S41, the resynchronizing signal output circuit 5 changes the output to a high level for a predetermined period, processing is returned to the step S40 and the same processing is repeated.
The resynchronizing signal output circuit 5 is changed to a high level for a predetermined period at timing at which a count value of the reference counter 3 is zero by the above processing. The resynchronizing signal output circuit outputs a resynchronizing signal shown in FIG. 23C.
Next, referring to the timing chart shown in FIG. 23, the above flowcharts will be described in the concrete. Suppose that a detected synchronizing signal shown in FIG. 23A is output by the synchronizing signal detecting circuit 1 shown in FIG. 19. When the zeroth detected synchronizing signal not shown is input to the synchronization judging circuit 1, it is judged in the step S1 that a synchronizing signal is detected (YES), processing proceeds to the step S2 and the reference counter 3 is reset. In the step S3, the value is the variable N.sub.1 is initialized to zero.
In the step S4, it is judged whether a synchronizing signal is detected or not. Assuming that a first synchronizing signal shown in FIG. 23A is input, it is judged in the step S4 that a synchronizing signal is detected (YES) and processing proceeds to the step S5. In the step S5, it is judged whether the value of the reference counter 3 is 990 or more or not. Assuming that the zeroth and first synchronizing signals are input in a normal cycle, while the processing in the steps 4 and 6 is repeated, a synchronizing signal is detected (YES) in the step S4 and processing proceeds to the step S5. In the step S5, it is judged that a synchronizing signal is detected in a window, processing is returned to the step S2 and the same processing is repeated.
Next, assuming that a second synchronizing signal is not detected due to anything at time for the second synchronizing signal to be detected, it is judged in the step S6 that a synchronizing signal is detected in a window (YES) and processing proceeds to the step S7.
In the step S7, the reference counter 3 is reset. At that time, in the resynchronizing signal output circuit 5, the processing shown in FIG. 22 is executed and as a result, at timing at which the reference counter 3 is reset (a count value is reset to zero), a resynchronizing signal (a pulse shown in FIG. 23C) is output.
Therefore, in the above prior example, a window signal is generated, a place for a synchronizing signal to be detected is instructed based upon a count value of the reference counter 3 and if a synchronizing signal is not detected in the place instructed by the window signal, the resynchronizing signal output circuit 5 outputs a resynchronizing signal. Therefore, as a synchronizing signal can be interpolated even if a synchronizing signal is not detected due to anything, data read from a recording medium can be regenerated.
A case in which a time lag is caused between timing at which a synchronizing signal is regenerated and timing at which a window signal is changed to a high level due to the jump of a track and others in the above conventional type resynchronizing device will be described.
If a third synchronizing signal shown in FIG. 23A is input at timing different from the pulse of a window signal shown in FIG. 23B, a regenerative synchronizing signal shown in FIG. 23C is not output at the timing at which the third detected synchronizing signal is input and is output at the same timing as a third window signal. Therefore, in that case, a time lag occurs between a detected synchronizing signal read from a recording medium and a regenerative synchronizing signal output from a resynchronizer.
In such a situation, in this prior example, when no synchronizing signal is detected sequentially four times at timing at which a window signal is changed to a high level, the window signal is kept at a high level and synchronization is again executed.
That is, in the flowchart shown in FIG. 20, if a case (a case in which a time lag occurs between the timing of a detected synchronizing signal and a window signal) in which it is judged that no synchronizing signal is detected (NO) in the step S4 and that no synchronizing signal is detected in a window in the step S6 continues four times or more (N.sub.1 .gtoreq.4), it is judged YES in the step S9, processing is returned to the step S1 and the reference counter 3 is reset. As a result, a window signal shown in FIG. 23B is kept at a high level until a sixth detected synchronizing signal is input.
As it is judged YES in the step S1, processing proceeds to the step S2 and a count value of the reference counter 3 is reset to zero when the sixth detected synchronizing signal is input, the timing of a window signal and a detected synchronizing signal is synchronous.
Therefore, as in the above conventional type resynchronizer, the timing of a detected synchronizing signal and a regenerative synchronizing signal is not synchronous for a period shown in FIG. 23D since the third detected synchronizing signal in which the jump of a track and others occur is input until the sixth detected synchronizing signal is input, there is a problem that data read from a recording medium cannot be precisely regenerated during the above period.